VHDL VHSIC Hardware Description Language Very High Speed Integrated Circuits VHDL-87 VHDL-93.

Apresentação em tema: "VHDL VHSIC Hardware Description Language Very High Speed Integrated Circuits VHDL-87 VHDL-93."— Transcrição da apresentação:

1 VHDL VHSIC Hardware Description Language Very High Speed Integrated Circuits VHDL-87 VHDL-93

2 reg4 d0 d1 d2 d3 en clk s0 s1 s2 s3 entity reg4 is port (d0, d1, d2, d3, en, clk : in bit; s0, s1, s2, s3 : out bit ); end entity reg4; entidade portas de entrada portas de saída declaração da entidade

3 A descrição da implementação interna duma entidade chama-se corpo arquitectural. Uma entidade pode ter vários corpos arquitecturais que correspondem às implementação alternativas. Corpo arquitectural comportamental descreve o funcionamento de um modo abstracto; só inclui atribuições de sinais concorrentes e processos que especificam acções sequenciais a executar. estrutural descreve que subsistemas compõem a entidade e como estes são interligados. misto algumas partes da entidade são descritas como comportamentais enquanto outras são descritas de modo estrutural.

4 Descrição comportamental architecture Behavioral of reg4 is begin process (d0, d1, d2, d3, en, clk) is begin if en = '1' and clk = '1' then s0 <= d0; s1 <= d1; s2 <= d2; s3 <= d3; end if; end process; end Behavioral;

5 Descrição estrutural bit0 s0 s latch d clk d0 bit1 s1 s latch d clk d1 bit2 s2 s latch d clk d2 bit3 s3 s latch d clk d3 gate z and2_gate x y en clk

6 Descrição estrutural entity latch is port ( d, clk : in bit; s : out bit); end latch; architecture beh of latch is begin latch_beh: process (clk, d) is begin if clk = '1' then s <= d; end if; end process latch_beh; end beh; entity and2_gate is Port ( x, y : in bit; z : out bit); end and2_gate; architecture beh of and2_gate is begin z <= x and y; end beh; bit0 s0 s latch d clk d0 bit1 s1 s latch d clk d1 bit2 s2 s latch d clk d2 bit3 s3 s latch d clk d3 z x y en clk and2_gate

7 Descrição estrutural entity latch is port ( d, clk : in bit; s : out bit); end latch; architecture beh of latch is begin process (clk, d) is begin if clk = '1' then s <= d; end if; end process; end beh; entity and2_gate is Port ( x, y : in bit; z : out bit); end and2_gate; architecture beh of and2_gate is begin z <= x and y; end beh; bit0 s0 s latch d clk d0 bit1 s1 s latch d clk d1 bit2 s2 s latch d clk d2 bit3 s3 s latch d clk d3 z x y en clk and2_gate

8 entity reg4 is Port ( d0, d1, d2, d3, en, clk : in bit; s0, s1, s2, s3 : out bit); end reg4; architecture estrutural of reg4 is signal int_clk : bit; begin bit0: entity work.latch(beh) port map (d0, int_clk, s0); bit1: entity work.latch(beh) port map (d1, int_clk, s1); bit2: entity work.latch(beh) port map (d2, int_clk, s2); bit3: entity work.latch(beh) port map (d3, int_clk, s3); gate: entity work.and2_gate(beh) port map (en, clk, int_clk); end estrutural; instâncias de componentes int_clk

9 library IEEE; use IEEE.std_logic_1164.all; entity design_module_ent is port ( input1,input2,input3,input4 : in STD_LOGIC; output1,output2,output3: out STD_LOGIC ); end design_module_ent; architecture design_module_ent_arch of design_module_ent is component and_ent port( input1,input2 : in STD_LOGIC; output1: out STD_LOGIC ); end component; begin logic_AND_1 : and_ent PORT MAP (input1,input2,output1); logic_AND_2 : and_ent PORT MAP (input2,input3,output2); logic_AND_3 : and_ent PORT MAP (input3,input4,output3); end design_module_ent_arch;

10 library IEEE; use IEEE.std_logic_1164.all; entity design_module_ent is port ( input1,input2,input3,input4 : in STD_LOGIC; output1,output2,output3: out STD_LOGIC ); end design_module_ent; architecture design_module_ent_arch of design_module_ent is component and_ent port( input1,input2 : in STD_LOGIC; output1: out STD_LOGIC ); end component; begin logic_AND_1 : and_ent PORT MAP (input1,input2,output1); logic_AND_2 : and_ent PORT MAP (input2,input3,output2); logic_AND_3 : and_ent PORT MAP (input3,input4,output3); end design_module_ent_arch; output1 output2 output3 input1 input2 input3 input4

11 library IEEE; use IEEE.std_logic_1164.all; entity adder1 is port ( A: in STD_LOGIC; B: in STD_LOGIC; SUM: out STD_LOGIC; CARRY: out STD_LOGIC ); end adder1; architecture adder1_arch of adder1 is begin -- > SUM <= A xor B; CARRY <= A and B; end adder1_arch; A B SUM CARRY

12 library IEEE; use IEEE.std_logic_1164.all; entity adder1 is port ( A: in STD_LOGIC; B: in STD_LOGIC; SUM: out STD_LOGIC; CARRY: out STD_LOGIC ); end adder1; architecture adder1_arch of adder1 is begin -- > SUM <= A xor B; CARRY <= A and B; end adder1_arch; library IEEE; use IEEE.std_logic_1164.all; entity ORGATE is port ( A: in STD_LOGIC; B: in STD_LOGIC; Z: out STD_LOGIC ); end ORGATE; architecture ORGATE_arch of ORGATE is begin -- > Z <= A or B; end ORGATE_arch; entity FULLADD is port (A, B, CIN : in bit; SUM, CARRY : out bit); end FULLADD; architecture STRUCT of FULLADD is signal I1, I2, I3 : bit; component adder1 port(A,B : in bit; SUM, CARRY : out bit); end component; component ORGATE port(A,B : in bit; Z : out bit); end component; begin u1:adder1 port map(A,B,I1,I2); u2:adder1 port map(I1,CIN,SUM,I3); u3:ORGATE port map(I2,I3,CARRY); end STRUCT; Z OR

13 entity FULLADD is port (A, B, CIN : in bit; SUM, CARRY : out bit); end FULLADD; architecture STRUCT of FULLADD is signal I1, I2, I3 : bit; component adder1 port(A,B : in bit; SUM, CARRY : out bit); end component; component ORGATE port(A,B : in bit; Z : out bit); end component; begin u1:adder1 port map(A,B,I1,I2); u2:adder1 port map(I1,CIN,SUM,I3); u3:ORGATE port map(I2,I3,CARRY); end STRUCT; A (A) B (B) SUM (I1) CARRY (I2) A (I1) B (CIN) SUM (SUM) CARRY (I3) OR I2 I3 CARRY (CARRY) A B CIN CARRY SUM

14 LED1 LED2 LED3 LED4 SW1 SW2 SW3

15 entity LCD_struc is Port ( switchers : in std_logic_vector(2 downto 0); LEDs : out std_logic_vector(3 downto 0); clk48 : in std_logic; rst : in std_logic); end LCD_struc; architecture Behavioral of LCD_struc is component LED_SW PORT (CLK,RESET,SW1,SW2,SW3: IN std_logic; LED1,LED2,LED3,LED4 : OUT std_logic); end component; component Divider Port ( clk48 : in std_logic; rst : in std_logic; loc_clk : out std_logic); end component; signal internal_clock : STD_LOGIC; begin FSM : Divider port map(clk48,rst,internal_clock); led_control : LED_SW port map(internal_clock,rst,switchers(2),switchers(1),switchers(0), LEDs(0),LEDs(1),LEDs(2),LEDs(3)); end Behavioral; switchers(2) switchers(1) switchers(0) Divider LED_SW clk48 rst loc_clk internal_clock CLK RESET SW1 SW2 SW3 LED1 LED2 LED3 LED4 LEDs(0) LEDs(1) LEDs(2) LEDs(3) LEDs : out std_logic_vector(3 downto 0); 48 MHz 1 Hz rst S3S3 S2S2 S1S1 L1L1 L2L2 L3L3 L4L4 LCD_struc switchers : in std_logic_vector (2 downto 0);

16 entity LCD_struc is Port ( switchers : in std_logic_vector(2 downto 0); LEDs : out std_logic_vector(3 downto 0); clk48 : in std_logic; rst : in std_logic); end LCD_struc; architecture Behavioral of LCD_struc is component LED_SW PORT (CLK,RESET,SW1,SW2,SW3: IN std_logic; LED1,LED2,LED3,LED4 : OUT std_logic); end component; component Divider Port ( clk48 : in std_logic; rst : in std_logic; loc_clk : out std_logic); end component; signal internal_clock : STD_LOGIC; begin FSM : Divider port map(clk48,rst,internal_clock); led_control : LED_SW port map(internal_clock,rst,switchers(2),switchers(1),switchers(0), LEDs(0),LEDs(1),LEDs(2),LEDs(3)); end Behavioral; connection switchers(2) switchers(1) switchers(0) Divider LED_SW clk48 rst loc_clk internal_clock CLK RESET SW1 SW2 SW3 LED1 LED2 LED3 LED4 LEDs(0) LEDs(1) LEDs(2) LEDs(3) LEDs : out std_logic_vector(3 downto 0); 48 MHz 1 Hz rst S3S3 S2S2 S1S1 L1L1 L2L2 L3L3 L4L4 LCD_struc switchers : in std_logic_vector (2 downto 0);

17 entity VHDL architecture entity my_gate is port ( x1: in STD_LOGIC; x2: in STD_LOGIC; x3: in STD_LOGIC; y: out STD_LOGIC ); architecture my_gate_arch of my_gate is begin -- > y <= not (x1 and x2 and x3); end my_gate_arch;

18 STD_LOGIC 1)'1'- logical 1 2)'0'- logical 0 3)'H' – weak 1 4)'L' – weak 0 5)'X' – unknown 6)'U' – uninitialized 7)'Z' – high impedance 8)'-' – don't care 9)'W' – weak unknown