Desenvolvimento da Eletrônica de Front End do HCAL/HF

Apresentação em tema: "Desenvolvimento da Eletrônica de Front End do HCAL/HF"— Transcrição da apresentação:

1 Desenvolvimento da Eletrônica de Front End do HCAL/HF
Reunião geral de grupo – UERJ – Julho 2013

2 Desenvolvimento da eletrônica de Front End do HF
Projeto UERJ-CBPF-UNICAMP Grupo de trabalho: Desenvolvimento/testes: Helio Nogima, Jhonatan Seilhe (IC - CBPF), Mario Vaz, A. Vilela Pereira, Alessandro Zachi Iniciando atividades: Dilson Damião, Wagner Carvalho (projeto correlacionado - módulos de calibração) + Estudantes CEFET (IC) Testes - projeto GBT (CERN): Diego Figueiredo Contato com empresas para produção: José Augusto Chinellato, Edmilson Manganote Coordenação: A. Santoro, G. Alves Colaboração com Tullio Grassi (CMS – HCAL) UERJ - Reunião de grupo

3 G. Alves – LISHEP 2013 UERJ - Reunião de grupo

4 HF Front End Readout Module
UERJ - Reunião de grupo

5 HF Front End Readout Module
G. Alves – LISHEP 2013 UERJ - Reunião de grupo

6 HF Front End RM card HF RM card prototype diagram (test beam)
UERJ - Reunião de grupo

7 QIE 10 UERJ - Reunião de grupo

8 QIE 10 UERJ - Reunião de grupo

9 QIE 10 UERJ - Reunião de grupo

10 QIE test stand (Fermilab)
UERJ - Reunião de grupo

11 HF Front End Readout Module
UERJ - Reunião de grupo

12 HF RM FPGA: Design UERJ - Reunião de grupo

13 HF RM FPGA: Design implementation
UERJ - Reunião de grupo

14 More in detail (“channel synchronizer”)
UERJ - Reunião de grupo

15 Design simulation: synchronization
QIE-12 QIEs Data QIE-1 QIE-12 QIEs Clock QIE-1 UERJ - Reunião de grupo

16 Design simulation: synchronization
QIE1 QIE2 QIE12 Synchronized Data UERJ - Reunião de grupo

17 Lab tests (development boards)
Single-Ended (or LVDS) M1A3PL1000 M1A3PL1000 QIE10 Emulator HF-FE FPGA design Single-Ended (or LVDS) Logic Analyzer Actel-Microsemi Cards for Hardware Tests of the Design UERJ - Reunião de grupo

18 Lab tests (development boards)
Synchronized Data QIE1 Byte 1 QIE1 Byte 2 QIE2 Byte 1 QIE2 Byte 2 Note: Acquisition in asynchronous mode for visualization. Same behavior as expected from simulation. Ouput from two QIEs synchronized to common clock (MClk). Input data read at rising and falling edge of each QIE clock (1st and 2nd bytes of QIE synchronized output) UERJ - Reunião de grupo

19 Test card design/production
A3P250L VQ100 CARD Top Side (Design/Assembling: Jhonatan Seilhe) Designed for tests of the PROASIC3L FPGAs behaviour under radiation (Tullio); 9 Cards produced and assembled; Cards will also be used for tests of the FE FPGA design using LVDS lines. UERJ - Reunião de grupo

20 LVDS transmission tests
UERJ - Reunião de grupo

21 Extras UERJ - Reunião de grupo

22 G. Alves – LISHEP 2013 UERJ - Reunião de grupo

23 G. Alves – LISHEP 2013 UERJ - Reunião de grupo

24 HF Multianode PMTs Without Clean-up With Clean-up
HF replacement PMTs have thinner windows, metal cases, and multiple anodes : tubes will be installed in LS1 All will help reduce impact of charged particles passing through the PMTs, as will the TDC capability of QIE10. Multianode techniques have been tested with both P5 and testbeam data Multianode and TDC capabilities require upgraded electronics Choice between 2-anode or 4-anode readout will be important as a cost driver and for engineering complexity Without Clean-up With Clean-up UERJ - Reunião de grupo

25 FE control module (ngCCM)
Requirements Good quality clock Orbit signal for data sync (QIERESET) Warning-test-enabled signal for calibration I2C communication for GBTX, QIE10 and FE-FPGA configuration Robustness  neighbor ngCCM can take control in case of failure G. Alves – LISHEP 2013 UERJ - Reunião de grupo

26 HF Front End RM prototype
UERJ - Reunião de grupo

27 QIE test stand (Fermilab)
E. Hughes – HCAL Upgrade meeting (23 May 2013) UERJ - Reunião de grupo

28 QIE test stand (Fermilab)
E. Hughes – HCAL Upgrade meeting (23 May 2013) UERJ - Reunião de grupo

29 QIE test stand (Fermilab)
E. Hughes – HCAL Upgrade meeting (23 May 2013) UERJ - Reunião de grupo

30 FPGA used resources (w/ SC)
UERJ - Reunião de grupo

31 FPGA I/Os (w/ SC) 4 are not part of the design
There are 3 missing lines 12 x QIE( Clk + Disc.) + MClk + GBTClk 12 x QIE (8 bit data lines) 3 x GBT (44 data lines) 12 x QIE Reset LVDS Inputs -> 244 pins LVDS Outputs -> 288 pins Inputs -> 29 pins Output -> 54 pins + I/O Total = 615 pins UERJ - Reunião de grupo

32 Jhonatan Seilhe, Mario Vaz
UERJ - Reunião de grupo

33 Jhonatan Seilhe, Mario Vaz
UERJ - Reunião de grupo