Introdução ao VHDL João M. P. Cardoso

Um Contador de 0 a 7 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity count is Port ( clk : in std_logic; reset : in std_logic; cnt : out std_logic_vector(2 downto 0)); end count; architecture Behavioral of count is signal cnt1 : std_logic_vector(2 downto 0); begin process(clk, reset) if reset = '1' then cnt1 <= (others => '0'); elsif clk'event AND clk = '1' then cnt1 <= cnt1 + 1; end if; end process; cnt <= cnt1; end Behavioral;

Simulação Descrição em VHDL de uma bancada de teste Instância o componente Define o valor dos sinais Só serve para simulação! Criação de um ficheiro do tipo Test Bench Waveform Permite a atribuição de valores aos sinais utilizando uma interface gráfica

Bancada de Teste BEGIN uut: count PORT MAP( clk => clk, LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS COMPONENT count PORT( clk : IN std_logic; reset : IN std_logic; cnt : OUT std_logic_vector(2 downto 0) ); END COMPONENT; SIGNAL clk : std_logic; SIGNAL reset : std_logic; SIGNAL cnt : std_logic_vector(2 downto 0); SIGNAL clock : std_logic := '0'; -- for simulation BEGIN uut: count PORT MAP( clk => clk, reset => reset, cnt => cnt ); clock <= not clock after 10 ns; -- T = 20ns clk <= clock; -- *** Test Bench - User Defined Section *** tb : PROCESS reset <= '1'; wait for 20 ns; reset <= '0'; wait for 200 ns; --wait; -- will wait forever END PROCESS; -- *** End Test Bench - User Defined Section *** END;

ModelSim XE II/Starter 5.7c Janela de ondas do simulador

Descodificador de Sete Segmentos architecture Behavioral of seven_seg is begin process(inp_data) case inp_data is when "0000" => out_data <= "10000001"; when "0001" => out_data <= "11001111"; when "0010" => out_data <= "10010010"; when "0011" => out_data <= "10000110"; when "0100" => out_data <= "11001100"; when "0101" => out_data <= "10100100"; when "0110" => out_data <= "10100001"; when "0111" => out_data <= "10001111"; when "1000" => out_data <= "10000000"; when "1001" => out_data <= "10000100"; when others => out_data <= "11111111"; end case; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity seven_seg is Port ( inp_data : in std_logic_vector(3 downto 0); out_data : out std_logic_vector(7 downto 0)); end seven_seg;

Exemplo: Máquina de Bebidas Disponibiliza a lata depois de 150 ou mais escudos terem sido depositados Uma única abertura para moedas (50$00 e 100$00) Não dá troco FSM da máquina de bebidas CEM CINQ Reset Clock Abre Sensor Moedas Mecanismo Libertar Lata

Exemplo: Máquina de Bebidas Tabela e Diagrama de Estados Tabela de estados Simbólica Estado Entrada Próx. Saída Actual CEM CINQ Estado open 0$ 0 0 0$ 0 0 1 50$ 0 1 0 100$ 0 1 1 – – 50$ 0 0 50$ 0 0 1 100$ 0 1 0 150$ 0 1 1 – – 100$ 0 0 100$ 0 0 1 150$ 0 1 0 150$ 0 1 1 – – 150$ – – 150$ 1 0$ Reset 50$ CINQ CEM + CINQ 100$ CEM 150$ [open]

Exemplo: Máquina de Bebidas fsm1: process(current_state, CEM, CINQ) begin case current_state is when zero => s_open <= '0'; if CINQ = '1' then next_state <= cinquenta; else next_state <= zero; end if; when cinquenta => if CINQ = '1' then next_state <= st_cem; elsif CEM = '1' then next_state <= cent_cinq; else next_state <= cinquenta; end if; when st_cem => if CINQ = '1' OR CEM = '1' then next_state <= cent_cinq; else next_state <= st_cem; end if; when cent_cinq => s_open <= '1'; next_state <= zero; when others => end case; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsm is Port ( clk : in std_logic; reset : in std_logic; CEM : in std_logic; CINQ : in std_logic; s_open : out std_logic); end fsm; architecture Behavioral of fsm is type state_type is (zero, cinquenta, st_cem, cent_cinq); signal current_state, next_state: state_type; begin fsm2: process(reset, clk) if reset = '1' then current_state <= zero; elsif clk'event AND clk='1' then current_state <= next_state; end if; end process;

Exemplo: Máquina de Bebidas Quantos Flip-Flops existem no hardware sintetizado? Modificar as directivas de síntese para utilizar o menor número de FFs possível 4 estados => 2 FFs