San Jose State University Department of Electrical Engineering December 11 Fall 2001 EE 166 PROJECT Prof. David Parent Group Members Khanh Quan, Thy tran,

Apresentação em tema: "San Jose State University Department of Electrical Engineering December 11 Fall 2001 EE 166 PROJECT Prof. David Parent Group Members Khanh Quan, Thy tran,"— Transcrição da apresentação:

1 San Jose State University Department of Electrical Engineering December 11 Fall 2001 EE 166 PROJECT Prof. David Parent Group Members Khanh Quan, Thy tran, Yan Wang,Cecilia Cheung 4BIT SERIAL TO PARALLEL CONVERTER

2 Outline Introduction Specifications Design Principle Results Conclusion

3 Introduction Functionality: Functionality:  Input a serial data stream  Output a 4 bit parallel bit stream Applications: Applications:  Serial to parallel converter

4 SPECIFICATION Design challenges Design challenges  Minimize clock skew  Worst case power used < 500 mW  V switching TH=2.5 V  Area < 1800 um x 1800 um  Able to drive a 10pF load at 10Mhz

5 DESIGN PRINCIPLE Design block diagram Design block diagram

6 Gate-level schematic

7 Parameters Inverter: Wn=4um Wp=9.6um Inverter: Wn=4um Wp=9.6um Nand_2: Wn=4um Wp=4um Nand_2: Wn=4um Wp=4um Nand_3: Wn=8 Wp=4um Nand_3: Wn=8 Wp=4um Output Buffer: Output Buffer: 1 st stage: Wn=4um Wp=9.6um 1 st stage: Wn=4um Wp=9.6um 2 nd stage: Wn=12.8um Wp=30.8um 2 nd stage: Wn=12.8um Wp=30.8um 3 rd stage: Wn=46.6 Wp=99.6um 3 rd stage: Wn=46.6 Wp=99.6um 4 th stage: Wn=133.6um Wp=320.6um 4 th stage: Wn=133.6um Wp=320.6um

8 4bit serial to parallel converter

9 Mask Layout

10 Simulated I/O waveforms

11 Conclusion  Achievements:  Problems:  Reasonable area  Vth= 2.42V