VHDL - Tipos de dados compostos e operações Arrays: Conjunto de valores de mesmo tipo, onde a posição de cada elemento é dado por um escalar Sintaxe: array_type_definition <= array ( discrete range {,...} of element_subtype_indication discrete range <= discrete_subtype_indication | simple_expression (to | downto) simple_expression subtype_indication <= type_mark [range simple_expression (to | downto) simple_expression]

VHDL - Tipos de dados compostos e operações - Array Exemplo1 type word is array (0 to 31) of bit; type word is array (31 downto 0) of bit; type controller_state is ( initial, idle, active,error) type state_counts is array (idle to error) of natural; type state_counts is array (controller_state range idle to error) of natural;

VHDL - Tipos de dados compostos e operações - Array Exemplo1- cont. subtype coeff_ram_address is integer range 0 to 63; type coeff_array is array ( coeff_ram_address) of real; variable buffer_register, data_register: word; variable counters: state_counts; variable coeff: coeff_array;

VHDL - Tipos de dados compostos e operações - Array Exemplo1- cont. Coef(0) := 0.0; counters(active) := counters(active) + 1; data_register := buffer_register;

VHDL - Tipos de dados compostos e operações - Array Exemplo2 entity coeff_ram is port(rd,wr : in bit; addr : in coeff_ram_address; d_in : in real; d-out : out real); end entity coeff_ram; Architecture abstract of coeff_ram is begin memory: process is type coeff_array is array(coeff_ram_address) of real; Variable coeff:coeff_array;

VHDL - Tipos de dados compostos e operações - Array Exemplo2 - cont. begin for index in coeff_ram_address loop coeff(index):= 0.0; end loop; loop wait on rd,wr, addr, d_in; if rd = ‘1’ then d_out <= coeff(addr); end if; if wr = ‘1’ then coeff(addr) <= d_in; end loop end process memory; end architecture abstract;

VHDL - Tipos de dados compostos e operações - Array Multidimensional Exemplo1 type symbol is ('a', 't', 'd', 'h', digit, cr, error); type state is range 0 to 6; type transition_matrix is array (state, symbol) of state; variable transition_table : transition_matrix; Transition_table(5,’d’);

VHDL - Tipos de dados compostos e operações - Array Multidimensional Exemplo2 type point is array (1 to 3) of real; type matrix is array ( 1 to 3, 1 to 3) of real; variable p,q : point variable transform : matrix; for i in 1 to 3 loop q(i) : = 0.0; for j in 1 to 3 loop q(i) := q(i) + transform(i,j) * p(j); end loop

VHDL - Tipos de dados compostos e operações - Array Agregado Sintaxe - associação posicional aggregate <= ( ( { choices =>] expression {,...} ) Exemplo type point is array (1 to 3) of real; constant origin : point := (0.0, 0.0, 0.0); variable view_point : point := (10.0, 20.0, 0.0);

VHDL - Tipos de dados compostos e operações - Array Agregado Sintaxe - associação por nome choice <= ( simple_expression | discrete_range | others {,...} ) Exemplo1 variable view_point : point := (1 => 10.0, 2 => 20.0, 3 => 0.0); type coeff_array is array (coeff_ram_addrress) of real varaible coeff : coeff_array := (0 => 1.6, 1=> 2.3 , 2=> 1.6, 3 to 63 => 0.0); varaible coeff : coeff_array := (0 => 1.6, 1=> 2.3 , 2=> 1.6, others => 0.0); varaible coeff : coeff_array := (0 | 2 => 1.6, 1=> 2.3, others =>0.0); varaible coeff : coeff_array := (1.6, 2.3 , 2=> 1.6, others =>0.0); -- illegal

VHDL - Tipos de dados compostos e operações - Array Agregado Exemplo2 - FSM de um controlador de modem ‘cr’ ‘a’ ‘t’ ‘d’ 1 2 3 digit 4 ‘h’ digit cr 5 6 error other

VHDL - Tipos de dados compostos e operações - Array Agregado Exemplo2 - FSM de um controlador de modem - cont modem_controller : process is type symbol is ( ‘a’, ‘t’, ‘d’, ‘h’, digit, cr, other); type symbol_string is array ( 1 to 20) to symbol; type state is range 0 to 6; type transtion_matrix is array ( state, symbol) of states; constant next_state: transation_matrix := ( 0 => (‘a’ => 1, others => 6), 1 => (‘t’ => 2, others => 6), 2 => (´’d’ => 3, ‘h’ => 5 , ithers => 6), 3 => (digit => 4 , others 6), 4 => (digit => 4 , cr => 0 , others 6), 5 => (cr => 0, others => 6), 6 => (cr => 0, others => 6),;

VHDL - Tipos de dados compostos e operações - Array Agregado Exemplo2 - FSM de um controlador de modem - cont variable command: symbol_string; variable current_state: state := 0; begin ..... for index in 1 to 20 loop current_state := next_state(current_state, commnad(index)); case current state is ...... end case; end loop; end process modem_controller;

VHDL - Tipos de dados compostos e operações - Array Agregado Agregado como target variable_assignment-statement <= [ label:] ( name | aggregate) := expression; Exemplo (z_flag,n_flag,v_flag,c_flag) <= fçlag_reg;

VHDL - Tipos de dados compostos e operações - Atributo de Array Atributos A’left(N) A’rirht(N) A’low(N) A’high(N) A’range(N) A’reverse_range(N) A’length(N) A’ascending(N) Exemplo type A is array ( 1 to 4 , 31 downto 0) of boolean; A’left(1) = 1 A’rirht(2) = 0 A’low(1) = 1 A’high(2) = 31 A’range(1) is 1 to 4 A’reverse_range(2) is 0 to 31 A’length(2) = 32 A’ascending(1) = true A’ascending(2) = false

VHDL - Tipos de dados compostos e operações - Tipos de Array Irrestrito Sintaxe: array_type_definition <= array ( type_mark range <> {,...}) of element_subtype_indication type sample is array (natural range <> ) of integer; subype long_sample is sample(0 to 255; variable short_sample_buf : sample(o to 63); variable new_sample_buf : long_sample(o to 63);

VHDL - Tipos de dados compostos e operações - Tipos de Array Irrestrito String Bit Vector Standart-Logic Arrays (std_logic_1164) String and Bit_String Literals type string is array (positive range <> ) of char; type bit_vector is array (natural range <> ) of bit; type std_ulogic_vector is array (natural range <> ) of std_ulogic; constant mensage : string := “Ready “ variable test : std_ulogic_vector(0 to 13) := “zzzzzzzzz----”

VHDL - Tipos de dados compostos entity and_multiple is port ( i : in bit_vector; y : out bit ); end entity and_multiple; architecture behavioral of and_multiple is begin and_reducer : process ( i ) is variable result : bit; result := '1'; for index in i'range loop result := result and i(index); end loop; y <= result; end process and_reducer; end architecture behavioral;

VHDL - Tipos de dados compostos subtype halfword is bit_vector(0 to 15); entity byte_swap is port (input : in halfword; output : out halfword); end entity byte_swap; architecture behavior of byte_swap is begin swap : process (input) output(8 to 15) <= input(0 to 7); output(0 to 7) <= input(8 to 15); end process swap; end architecture behavior;

VHDL - Tipos de dados compostos Records type time_stamp is record seconds : integer range 0 to 59; minutes : integer range 0 to 59; hours : integer range 0 to 23; end record time_stamp; variable sample_time, current_time : time_stamp; constant midday : time_stamp := (0, 0, 12); constant clock : integer := 79; variable sample_hour : integer; current_time := (30, 15, 2); sample_time := current_time; sample_hour := sample_time.hours; current_time.seconds := clock mod 60;

architecture system_level of computer is type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, nop); type reg_number is range 0 to 31; constant r0 : reg_number := 0; constant r1 : reg_number := 1; constant r2 : reg_number := 2; -- . . . type instruction is record opcode : opcodes; source_reg1, source_reg2, dest_reg : reg_number; displacement : integer; end record instruction; type word is record instr : instruction; data : bit_vector(31 downto 0); end record word; signal address : natural; signal read_word, write_word : word; signal mem_read, mem_write : bit := '0'; signal mem_ready : bit := '0';

begin cpu : process is variable instr_reg : instruction; variable PC : natural; -- other declarations for register file, etc. address <= PC; mem_read <= '1'; wait until mem_ready = '1'; instr_reg := read_word.instr; mem_read <= '0'; wait until mem_ready = '0'; PC := PC + 4; case instr_reg.opcode is -- execute the instruction -- . . . when others => null; -- ..... end case; end process cpu;

memory : process is type memory_array is array (0 to 2**14 - 1) of word; variable store : memory_array := ( 0 => ( ( ld, r0, r0, r2, 40 ), X"00000000" ), 1 => ( ( breq, r2, r0, r0, 5 ), X"00000000" ), -- . . . 40 => ( ( nop, r0, r0, r0, 0 ), X"FFFFFFFE"), others => ( ( nop, r0, r0, r0, 0 ), X"00000000") ); begin wait until mem_read = '1'; read_word <= store(address); mem_ready <= '1'; wait until mem_read = '0'; mem_ready <= '0'; end process memory; end architecture system_level;