Verilog HDL

Introduzida em 1985 pela Gateway Design System Corporation Após 1990, passou a ser de domínio público, e em 1995 passou a ser padrão IEEE

Verilog HDL vs. VHDL Verilog HDL é mais próxima a C VHDL é mais próxima a ADA Considerada mais fácil de aprendizado, pois necessita de menos código para especificar projeto

Níveis de Especificação High level RTL Gate level Switch level

module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule

module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule … 20 $stop

module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule … 20 $stop A=0 $display $monitor

module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule … 20 $stop A=A+1 $monitor

module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule … 20 $stop B[0:3] = … $monitor

module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule … 20 $stop C = &A[6:7] $monitor

module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule … 20 $stop A=A+1 … $monitor

module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule … 20 $stop B[0:3] = … … $monitor

module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule … … 20 $stop C = &A[6:7] $monitor

module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule … 20 $stop

Resultado do Primeiro Exemplo Time A B C xxxxxxxx x xxxxxxxx x xxxx x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0 Stop at simulation time 20

Números e Comentários 549 // decimal number 'h 8FF // hex number 'o765 // octal number 4'b11 // 4-bit binary number 'b10x // 3-bit binary number with least /* significant bit unknown */ 5'd3 // 5-bit decimal number -4'b11 // 4-bit two's complement of 0011

Descrição em Verilog HDL module ( ); endmodule inputs outputs inouts

Descrição em Verilog HDL module ( ); endmodule regs + wires memories functions + tasks

initial + always assinalamentos contínuos instâncias de módulos Descrição em Verilog HDL module ( ); endmodule

Exemplos module NAND(in1, in2, out); input in1, in2; output out; // continuous assign statement assign out = ~(in1 & in2); endmodule

Exemplos module AND(in1, in2, out); // Structural model of AND gate from two NANDS input in1, in2; output out; wire w1; // two instantiations of the module NAND NAND NAND1(in1, in2, w1); NAND NAND2(w1, w1, out); endmodule

Exemplos module test_AND; reg a, b; wire out1, out2; initial begin // Test data a = 0; b = 0; #1 a = 1; #1 b = 1; #1 a = 0; end initial begin $monitor("Time=%0d a=%b b=%b out1=%b out2=%b", $time, a, b, out1, out2); end AND gate1(a, b, out2); NAND gate2(a, b, out1); endmodule

Referências e Concatenações initial begin: int1 A = 8'b ; B = {A[0:3] | A[4:7], 4'b0000}; end C = {2{4'b1011}}; //C = 8'b C = {{4{A[4]}}, A[4:7]}; // first 4 bits are sign extended

Memórias reg [31:0] Mem [0:1023]; A = Mem[0]; B = A[3:1]; Memória de 1024 posições de 32 bits

Operações Operações similares a C ~ Bitwise negation & Bitwise AND | Bitwise OR ^ Bitwise XOR ~& Bitwise NAND ~| Bitwise NOR ~^ or ^~ Equivalence Bitwise NOT XOR

Operações Unárias & AND | OR reduction ^ XOR reduction ~& NAND reduction ~| NOR reduction ~^ XNOR reduction

Operações

Fluxo de Controle if (A == 4) begin B = 2; end else begin B = 4; end case(address) 0 : $display ("It is 11:40PM"); 1 : $display ("I am feeling sleepy"); 2 : $display ("Let me skip this tutorial"); default : $display ("Need to complete"); endcase

Fluxo de Controle for(i = 0; i < 10; i = i + 1) begin $display("i= %0d", i); end i = 0; while(i < 10) begin $display("i= %0d", i); i = i + 1; end repeat (5) begin $display("i= %0d", i); i = i + 1; end

Controle de Tempo Delay  #10 a = 3; Ocorrência de eventos (posedge clock2) A = B&C; (A or B or C) D = A + B + C;

Projeto RTL Register Transfer Level Componentes básicos  Blocos lógicos combinacionais  Unidades funcionais  MUXes  Memórias  Registradores

Projeto RTL Blocos Lógicos Combinacionais or b or c) begin case (a) 2’b00: d = b + c; 2’b01: d = b – c; 2’b10: d = b * c; 2’b11: d = b / c; endcase end d + b c - b c * c b c b /

Projeto RTL Registradores (posedge clk) d = a; DQ clk da

Projeto RTL Registradores (posedge clk) begin case (a) 2’b00: d = b + c; 2’b01: d = b – c; 2’b10: d = b * c; 2’b11: d = 0; endcase end b c - b c * c b 0 DQ clk d

Projeto RTL Memória reg [15:0] R [0:7]; AD[3:0] DI[15:0] WR DO[15:0]

module uRISC; reg [15:0] PC; reg IF, ID, EX, WB, CLK; (posedge CLK) {IF,ID,EX,WB} = {WB,IF,ID,EX}; (posedge CLK) PC = (IF)?PC+1:PC; initial begin IF = 1; ID = 0; EX = 0; WB = 0; PC = 0; CLK = 0; $display("%10d: CLK=%d IF=%d ID=%d...", $time,CLK,IF,ID,EX,WB,PC); forever begin #10 CLK = 1; # 0 $display("%10d: CLK=%d IF=%d ID=%d...", $time,CLK,IF,ID,EX,WB,PC); #10 CLK = 0; # 0$display("%10d: CLK=%d IF=%d ID=%d...", $time,CLK,IF,ID,EX,WB,PC); if ($time > 100) $finish; end endmodule

Referências