MC542 Organização de Computadores Teoria e Prática 2006 Prof. Paulo Cesar Centoducatte ducatte@ic.unicamp.br www.ic.unicamp.br/~ducatte Review today, not so fast in future

MC542 Circuitos Lógicos Tecnologia de Implementação “Fundamentals of Digital Logic with VHDL Design” - (Capítulo 3) Review today, not so fast in future

Tecnologia de Implementação Sumário Introdução Transistor Como Chave Portas Lógicas NMOS Portas Lógicas CMOS Lógica Positiva e Negativa Chips Padrões Gate Array e FPGAs CMOS: Fabricação e Comportamento

Introdução Valores Lógicos como Voltagem

NMOS transistor as a switch Transistor como Chave x = "low" x = "high" A simple switch controlled by the input x MOSFET: Metal oxide semiconductor field-effect transistor Gate Source Drain Substrate (Body) NMOS transistor MOSFET: NMOS e PMOS V G V V S D Simplified symbol for an NMOS transistor NMOS transistor as a switch

PMOS transistor as a switch Transistor como Chave x = "high" x = "low" A switch with the opposite behavior of Figure 3.2 Gate Drain Source V DD Substrate (Body) PMOS transistor V G V V S D Simplified symbol for an PMOS transistor PMOS transistor as a switch

Comportamento dos Transistores NMOS e PMOS em Circuitos V V = 0 V V D D D V G V = 0 V S Closed switch Open switch Transistor NMOS when V = V when V = 0 V G DD G V = V S DD V V DD DD V G V D V V = V D D DD Open switch Closed switch Transistor PMOS when V = V when V = 0 V G DD G

Portas Lógicas com NMOS V DD x f R R + 5 V V f - V f V V x x x f Circuit diagram Graphical symbols Simplified circuit diagram A NOT gate built using NMOS technology

Portas Lógicas com NMOS (NAND) V DD x 1 f x 2 x x 1 2 f V f 1 V x 1 1 1 1 1 1 1 V x x 2 1 f x 2 Circuito Símbolo grafico Tabela Verdade

Portas Lógicas com NMOS (NOR)

Portas Lógicas com NMOS (AND) V V DD DD x 1 f x 2 V f x x f 1 2 A 1 V x 1 1 1 1 1 x 1 V f x x 2 2

Portas Lógicas com NMOS (OR)

Estrutura de um circuito NMOS

Estrutura de um Circuito CMOS (NMOS + PMOS) A função é implementada por uma rede Nmos e uma Pmos simultaneamente

NOT CMOS V DD T 1 x T T f 1 2 V V x f on off 1 1 off on T 2

NAND CMOS f = x1 + x2 PUN PDN f = x1.x2

NOR CMOS f = x1.x2 PUN PDN f = x1+x2

AND CMOS

Exemplo: Circuito Complexo f = x1 + x2 x3

Exercício Qual a função implementada por: f = x1 (x2x3 + x4)

Níveis de Tensão no Circuito

Lógica Positiva e Negativa x x f 1 2 1 x 1 1 1 f x 2 1 1 V V V x x f 1 1 1 2 L L H Logica Positiva: Tabela Verdade e Porta L H H H L H H H L x x f 1 2 Níveis de Tensão 1 1 x 1 1 f x 2 1 1 Logica Negativa: Tabela Verdade e Porta

Lógica Positiva e Negativa x x f 1 2 x 1 1 f x 2 1 1 1 1 V V V x x f 1 2 Logica Positiva: Tabela Verdade e Porta L L L L H L H L L H H H x x f 1 2 Níveis de Tensão 1 1 1 x 1 1 1 f x 1 1 2 Logica Negativa: Tabela Verdade e Porta

Chips Padrões Dual-inline package V DD Gnd Structure of 7404 chip

Implementation of f = x1x2 + x2x3 V DD 7404 7408 7432 x 1 x 2 x 3 f Implementation of f = x1x2 + x2x3

Sea-of-gates Gate Array

Gate Array

FPGA Field-Programmable Gate Array Logic block Interconnection switches I/O block I/O block I/O block I/O block

FPGA: Logic Block LUT – lookup table (a) Circuit for a two-input LUT x 1 2 f 0/1 (b) + = (c) Storage cell contents in the LUT

FPGA LUT x 1 x 2 0/1 0/1 0/1 0/1 f 0/1 0/1 0/1 0/1 x 3

FPGA Out D Q Clock Select Flip-flop In 1 2 3 LUT

FPGA

CMOS: Fabricação e Comportamento Transistor Nmos - off V = V G SiO 2 V = V S V D ++++++ ++++ ++++++ ++++++ +++ ++++++ ++++++ ++++++ ++++++ ++++++ +++++++++++ ++++++ ++++++ +++++++++++ +++++++++ Substrate (type p) +++++++++ Source (type n) Drain (type n) When V = 0 V, the transistor is off GS

CMOS: Fabricação e Comportamento V DD Transistor Nmos - on V = 5 V G SiO 2 V = V S V = V D ++++++ ++++ +++ ++++++ ++++++ ++++++ +++++++++++ +++++++++++++++++ +++++++++ ++ +++++++ ++++++++++ Channel (type n) When V = 5 V, the transistor is on GS

Current-voltage relationship in the NMOS transistor Transistor Nmos I D Triode Saturation V – V GS T V DS Current-voltage relationship in the NMOS transistor

Tensões em um Not Nmos V V R V I V = V V R (a) NMOS NOT gate (b) V DD DD R V f I V = V stat f OL V R x DS (a) NMOS NOT gate (b) V = 5 V x

Transferência de Voltagem Not Cmos = V OH DD Slope = – 1 V = V OL V V V ( V – V ) V T IL IH DD T DD V x V — DD 2

Margem de Ruído e Capacitância NML = VIL - VOL 1 2 A x f NMH = VOH - VIH NOT gate driving another NOT gate V V DD DD V A V x V f C The capacitive load at node A

Margem de Ruído e Capacitância Propagation delay V DD Gnd x A 50% 90% 10% t r f

Transistor MOS

Consumo de Potência V Current flow when input V DD V I x D I D V V f f V x Current flow when input V Current flow when input V x x changes from 0 V to 5 V changes from 5 V to 0 V

Passagem de 1s e 0s em MOS V V B A transistor NMOS transistor PMOS DD

Implementação “pobre” de um AND CMOS Logic Logic V f Voltage value value V x x V f x 1 2 f 1 1.5 V V 1 1.5 V V DD x 1 1.5 V 2 1 1 3.5 V 1 AND gate circuit Truth table and voltage levels

Fan-IN V f DD x 2 1 3 k R = r1 + r2 + …. + rk Vf Atraso “0”

Fan-Out inverter that drives n other inverters 1 V f f To inputs of To inputs of x x n other inverters n other inverters C n inverter that drives n other inverters Equivalent circuit for timing purposes V for n = 1 f V DD V for n = 4 f Gnd Time Propagation times for different values of n

Implementation of a buffer V DD V x V f Implementation of a buffer x f Graphical symbol

Tri-state tri-state buffer Equivalent circuit Truth table e = 0 x e f = 1 x f tri-state buffer Equivalent circuit e x f e Z 1 Z x f 1 1 1 1 Truth table Implementation

Tri-state e e x f x f (a) (b) e e x f x f (c) (d)

Uso de tri-state x f 1 s x 2

Transmission Gates s s f x f Z 1 x s Truth table Circuit s = x f = Z s Z 1 x s Truth table Circuit s = x f = Z s x f s = 1 x f = x s Equivalent circuit Graphical symbol

XOR x x f = x Å x 1 1 x 1 1 f = x Å x x 1 1 Truth table 2 1 2 1 1 x 1 1 1 f = x Å x x 1 2 1 1 2 Truth table Graphical symbol x 1 x 2 f = x Å x 1 2

XOR – Transmission Gate 1 x 2 f = x Å x 1 2

Mux – Transmission Gate 1 s x f 2